High sensitivity and low noise are important characteristics of high performance accelerometers since they determine the accelerometer's signal to noise ratio (SNR). Signal to noise ratio indicates directly the resolution or how small of an acceleration signal the accelerometer is able to detect.
The dominant mechanical noise source for a micromachined accelerometer is the molecular Brownian motion. To achieve thermal mechanical noise below 1 μg/√Hz and high sensitivity per unit footprint for capacitive accelerometers, efforts have been made toward realizing both large proof-mass, while efforts at increasing the sensitivity to acceleration of a capacitive accelerometer focused on increasing the capacitive sensitivity of the accelerometer by increasing the area and reducing the size of the capacitive gap through creating a high aspect-ratio gap. Increasing the proof-mass size has proven to be the most effective way to reduce the noise. While the sensing gaps need to be reasonably narrow to provide higher sensitivity without compromising the noise performance (increase the air damping).
With the existing technologies, the MEMS device footprint has to be increased to allow for large proof-mass and sense area because the device height is typically limited to ≤500 μm. Silicon on glass (SOG) and CMOS MEMS capacitive accelerometers that demonstrated <10 μg/√Hz noise floor have limited proof-mass thickness, typically <150 μm and 5 μm respectively. Thus device footprint has to be increased. A HARPSS-SOI process has also been used to increase proof-mass by utilizing the silicon mass on the backside of the SOI handle wafer (400 μm). Although a noise floor of 200 ng/√Hz is reported, the device footprint is large (49 mm2). There is a need for multi-axis accelerometers with small footprint and sub-μg resolution based on robust CMOS-compatible fabrication technology.
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